Intel Corp. announced that it will begin producing its next-generation Penryn processors by the end of 2007. The chip will use greater power efficiency to push improved Core 2 and Xeon chips to speeds over 3 GHz, Intel said Wednesday.
Intel’s new chip family indicates an important step in Intel’s “tick-tock” product strategy, which is the company’s schedule for delivering either a new chip architecture or smaller chip design on a yearly basis. This is according to Pat Gelsinger, general manager of Intel’s digital enterprise group at a press conference in San Francisco.
Intel CEO Paul Otellini apologized to investors March 5 for slacking off the development pace and pointed to the tick-tock model as Intel’s way for regaining market share it has lost to rival AMD.
Intel plans to make a big splash in the chip market with their new product family and will begin production of six Penryn processors, the dual-core and quad-core desktop chips, a dual-core notebook chip, dual-core and quad-core server chips, and a high-end server chip.
The Penryn will have smaller Core microarchitecture from chips using 65 nanometer feature sizes to 45 nanometer.
The Penryn Chip will also have better power management than previous Intel processors. Intel intends to run its new chips faster than 3GHz for the desktop and notebook versions.
Intel will also use 50 percent more on-chip memory in the new chip than the Core 2 Duo, which will allow them to hold more data on the chip. Dual-Core Penryn chips will have 6mb of Level 2 cache. Quad-core versions will have 12mb.
The improvements will make a chip that packs twice as many transistors into a space 25 percent smaller than the 65-nm processors.
Intel also plans to upgrade its Core microarchitecture to a new “Nehalem” design in 2008. It will be built first on 45nm architecture chips and then on a 3-2nm “Westmere” version in 2009. 2010 will see the “Gesher.”
“We view [Nehalem] as the first dynamically scalable microarchitecture,” Gelsinger said.
Nehalem will provide another huge leap in processing power by assigning two computing threads to each core, resulting in 16 threads for an eight-core chip that could deliver very fast performance.
The Nehalem also will have an on-die integrated memory controller, which is a feature that AMD claims to have first used in 2003 with its Direct Connect Architecture design.
Gelsinger did acknowledge the similarity between the two but said that both companies had come to the same conclusion.